Conductive vias, in the form of “through-substrate vias” (TSVs) or “through-wafer interconnects” (TWIs), typically interconnect with circuitry on the front side, or active surface, of a semiconductor device and extend to a location on the opposite, back side of the semiconductor device (e.g., to contact pads, such as ball pads, pads that facilitate die-to-die interconnection, bond pads, etc.) where electrical connections with the circuitry on the active surface may be established. TSVs are useful for assembling semiconductor devices in compact stacked, or three-dimensional (3D), arrangements.
A number of existing processes have been developed to fabricate conductive vias structured as through-wafer interconnects, to route electrical signals through semiconductor devices. These processes conventionally fall into two categories, depending upon the point in which they are effected during semiconductor device fabrication. More specifically, conventional categorization of conductive via fabrication processes depends upon whether conductive vias are fabricated before or during so-called “back-end-of-the-line” (BEOL) processing or after BEOL processing. BEOL processing involves the interconnection of the active components of a semiconductor device, and includes the fabrication of dielectric layers, conductive interconnects or plugs, conductive traces or wiring, and electrodes, or contact pads, by which the semiconductor device may be externally connected with other electronic components.
Conductive vias that are fabricated before or during BEOL processing typically have diameters (or other, equivalent lateral dimensions for non-cylindrical vias) of about 3 μm to about 5 μm. With current dry etch processes, via holes having height-aspect ratios (e.g., diameter to depth) of up to about 5:1 are achievable, meaning that via holes may extend only about 25 μm into the active surface of a semiconductor substrate under fabrication. Unfortunately, with current technology, such fabrication substrates that are only 25 μm thick cannot support many types of semiconductor devices, including dynamic random access memory (DRAM) devices.
Much longer (e.g., 150 μm) conductive vias may be fabricated after BEOL processing. Such conductive vias typically have height-aspect ratios of about 3:1. As a consequence, their diameters (or other, equivalent lateral dimensions) are relatively large (e.g., about 50 μm for a 150 μm long via). Thus, such conductive vias consume an undesirably large amount of surface area, or “real estate,” on the active surface of a fabrication substrate and unnecessarily limit or complicate design rules for the integrated circuitry that is to be fabricated on the active surface of a semiconductor device.